U-Boot 2009.01 Driver

admin 1/7/2022
  • U-Boot 2009.01 (Sep 17 2009 - 17:41:56) I2C: ready DRAM: 64 MB In: serial Out: serial Err: serial ARM Clock: 300000000 Hz DDR Clock: 150000000 Hz Net: Ethernet PHY: GENERIC @ 0x00. Hit any key to stop autoboot: 0 U-Boot printenv ethaddr ethaddr=00:08:ee:03:d6:ca U-Boot sf probe 0 8192 KiB M25P64 at 0:0 is now current device.
  • U-Boot Source Code. The current source code is available through the git repository at gitlab.denx.de.; Released Versions (and some special snapshots) are available from the DENX file server through HTTPS or FTP.; gitlab.denx.de also hosts the Custodian git trees; you can see the list of all custodian repositories here.; An attempt to collect a list of all U-Boot authors can be found here.
U-boot 2009.01 driver win 7

U-boot 2009.01 Driver Download

U-Boot

U-Boot for i.MX51 Based Designs, Rev. 0 Freescale Semiconductor 3 Getting the U-Boot Source Code 3 Getting the U-Boot Source Code The U-Boot source code is sent along with the Linux Board Support Package (BSP) for the i.MX51 EVK. U-Boot for i.MX51 Based Designs, Rev. 0 Freescale Semiconductor 3 Getting the U-Boot Source Code 3 Getting the U-Boot Source Code The U-Boot source code is sent along with the Linux Board Support Package (BSP) for the i.MX51 EVK. For the hardware version with 1 USB port! - Solve file permission problem when Web Access published folder is restricted by Active Directory Domain. VERSION=1.09-0.02 BOOT=1.13 KERNEL=2009/01/21 10:34:23 INITRD=2009/01/21 10:34:47 ROOTFS=2009/01/21 10:35:38 FILEBOOT = u-boot.

Mar 17th, 2018
U-Boot 2009.01 Driver

U-boot 2009.01 Drivers

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U-boot 2009.01 Driver Ed

  1. ar7100_ddr_initial_config(269) exit!
  2. sri
  3. WRT160NL u-boot version: 1.0.0
  4. Reserving 277k for U-Boot at: 81fb8000
  5. Reserving 44 Bytes for Board Info at: 81f87fd4
  6. Reserving 128k for boot params() at: 81f67fb0
  7. Now running in RAM - U-Boot at: 81fb8000
  8. flash size 8MB, sector count = 128
  9. *** Warning - bad CRC, using default environment
  10. In: serial
  11. Err: serial
  12. ag7100 get ethaddr for device eth0
  13. --------***** Get the RTL8306SD Manufactory ID=34dc *****-------
  14. Reg5: speed=0 nway=0 duplex=0
  15. Reg1: a1=7fd9 a2=2890 a3=115c a4=2890
  16. Reg1: a1=7fd9 a2=2890 a3=115c a4=2890
  17. eth0: 00:23:69:ed:9f:ad
  18. eth0
  19. ## Booting image at bf04003c ...
  20. Created: 2018-01-26 17:09:26 UTC
  21. Image Type: MIPS Linux Kernel Image (gzip compressed)
  22. Load Address: 80060000
  23. Verifying Checksum ... OK
  24. kernel: org len = 1209269, new len = 1245184
  25. ## Transferring control to Linux (at address 80060000) ...
  26. Copyright (C) 2011 Gabor Juhos <[email protected]wrt.org>
  27. Starting kernel at 80060000...
  28. [ 0.000000] Linux version 3.18.91 ([email protected]) (gcc version 4.8.3 (Ope nWrt/Linaro GCC 4.8-2014.04 unknown) ) #4 Fri Jan 26 18:05:42 CET 2018
  29. [ 0.000000] CPU0 revision is: 00019374 (MIPS 24Kc)
  30. [ 0.000000] Determined physical RAM map:
  31. [ 0.000000] Initrd not found or empty - disabling initrd
  32. [ 0.000000] Normal [mem 0x00000000-0x01ffffff]
  33. [ 0.000000] Early memory node ranges
  34. [ 0.000000] Initmem setup node 0 [mem 0x00000000-0x01ffffff]
  35. [ 0.000000] Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
  36. [ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
  37. [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pag es: 8128
  38. [ 0.000000] Kernel command line: board=WRT160NL console=ttyS0,115200 rootfst ype=squashfs,jffs2 noinitrd
  39. [ 0.000000] PID hash table entries: 128 (order: -3, 512 bytes)
  40. [ 0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
  41. [ 0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
  42. [ 0.000000] Readback ErrCtl register=00000000
  43. [ 0.000000] Memory: 28260K/32768K available (2643K kernel code, 148K rwdata, 552K rodata, 232K init, 193K bss, 4508K reserved, 0K cma-reserved)
  44. [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  45. [ 0.000000] Clocks: CPU:400.000MHz, DDR:400.000MHz, AHB:200.000MHz, Ref:5.000 MHz
  46. [ 0.000000] Calibrating delay loop... 265.42 BogoMIPS (lpj=1327104)
  47. [ 0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
  48. [ 0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
  49. [ 0.100000] MIPS: machine is Linksys WRT160NL
  50. [ 0.660000] NET: Registered protocol family 2
  51. [ 0.660000] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
  52. [ 0.660000] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
  53. [ 0.670000] TCP: Hash tables configured (established 1024 bind 1024)
  54. [ 0.680000] UDP hash table entries: 256 (order: 0, 4096 bytes)
  55. [ 0.690000] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
  56. [ 0.700000] futex hash table entries: 256 (order: -1, 3072 bytes)
  57. [ 0.710000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  58. [ 0.720000] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORIT Y) (c) 2001-2006 Red Hat, Inc.
  59. [ 0.740000] io scheduler noop registered
  60. [ 0.740000] io scheduler deadline registered (default)
  61. [ 0.740000] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled
  62. [ 0.780000] serial8250.0: ttyS0 at MMIO 0x18020000 (irq = 11, base_baud = 125 00000) is a 16550A
  63. [ 0.790000] console [ttyS0] enabled
  64. [ 0.790000] bootconsole [early0] disabled
  65. [ 0.800000] m25p80 spi0.0: found mx25l6405d, expected m25p80
  66. [[ 82.590000] random: nonblocking pool is initialized

U-boot 2009.01 Driver Win 7

U-boot 2009.01 driver win 7
Dear All
Im tryin to write a SPI Driver in u-boot-1.3.4 with SPI BUS 1 support for my processor AT91SAM9261 . I have defined the base macro for SPI bus 1 AT91SAM9261_BASE_SPI1 in /asm/arch/hardware.h and i av passed the bus id and chip select id . but im not getting any data or clock value on the pins . can any body let me what stupid mistake im committing? below is my source
#include <common.h>
#include <spi.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h
#include <asm/arch/at91_spi.h>
#include 'atmel_spi.h'
void spi_init()
{
/* do some initialization of SPI bus pins*/
at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_NPCS01 */
at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
/* Reset the SPI */
//spi_writel(ATMEL_SPI_SWRST, ATMEL_SPI_CR,1);
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct atmel_spi_slave *as;
unsigned int scbr;
u32 csrx;
void *regs;
max_hz=15000000;/* modified for AMOLED*/
mode=ATMEL_SPI_MR_MSTR;
mode =0;/* falling edge of clock spi XFER*/
bus=AT91SAM9261_ID_SPI1;
cs=AT91_PIN_PA25;/* chip select of the slave connected to . */
if (cs > 3 !spi_cs_is_valid(bus, cs))
return NULL;
regs = (void *)AT91SAM9261_BASE_SPI1; /* spi bus 1 ID of the */
/* Reset the SPI */
spi_writel(as,ATMEL_SPI_CR,ATMEL_SPI_SWRST);
scbr = (AT91_MASTER_CLOCK/max_hz)<<8; /* configure serial clock baud rate*/
if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
/* Too low max SCK rate */
return NULL;
if (scbr < 1)
scbr = 1;
csrx = ATMEL_SPI_CSRx_SCBR(scbr);
csrx = ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
if (!(mode & SPI_CPHA))
csrx = ATMEL_SPI_CSRx_NCPHA;
if (mode & SPI_CPOL)
csrx = ATMEL_SPI_CSRx_CPOL;
as = malloc(sizeof(struct atmel_spi_slave));
if (!as)
return NULL;
as->slave.bus = bus;
as->slave.cs = cs;
as->regs = regs;
as->mr = ATMEL_SPI_MR_MSTR ATMEL_SPI_MR_MODFDIS
ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
as->mr = ATMEL_SPI_CSRx_NCPHA ATMEL_SPI_CSR(2) ATMEL_SPI_MR_MSTR ;/* configure chipselect*/
spi_writel(as, CSR(cs), csrx);
return &as->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
free(as);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
/* Enable the SPI hardware */
spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
/*
* Select the slave. This should set SCK to the correct
* initial state, etc.
*/
spi_writel(as, MR, as->mr);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
/* Disable the SPI hardware */
spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
unsigned int len_tx;
unsigned int len_rx;
unsigned int len;
int ret;
u32 status;
unsigned short mask ;
const u8 *txp = dout;
u8 *rxp = din;
u8 value;
unsigned int pol;
bitlen=8;
ret = 0;
if (bitlen 0)
/* Finish any previously submitted transfers */
goto out;
/*
* TODO: The controller can do non-multiple-of-8 bit
* transfers, but this driver currently doesn't support it.
*
* It's also not clear how such transfers are supposed to be
* represented as a stream of bytes...this is a limitation of
* the current SPI interface.
*/
if (bitlen % 8) {
/* Errors always terminate an ongoing transfer */
flags = SPI_XFER_END;
goto out;
}
len = bitlen / 8;
/*
* The controller can do automatic CS control, but it is
* somewhat quirky, and it doesn't really buy us much anyway
* in the context of U-Boot.
*/
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
for (len_tx = 0, len_rx = 0; len_rx < len; ) {
status = spi_readl(as, SR);
if (status & ATMEL_SPI_SR_OVRES)
return -1;
if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
if (txp)
value = *txp++;
else
value = 0;
udelay(500000);
pol=spi_claim_bus(slave);
spi_writel(as, TDR, value); /*write data into device */
spi_release_bus(slave)
len_tx++;
if (status & ATMEL_SPI_SR_RDRF) {
value = spi_readl(as, RDR);
if (rxp)
*rxp++ = value;
len_rx++;
}
}
out:
if (flags & SPI_XFER_END) {
/*
* Wait until the transfer is completely done before
* we deactivate CS.
*/
do {
status = spi_readl(as, SR);
} while (!(status & ATMEL_SPI_SR_TXEMPTY));
//spi_writel(as,ATMEL_SPI_CSRx_CSAAT, value);
spi_cs_deactivate(slave);
}
return 0;
}